With the amount of new subnets being added it can be hard to get up to date information across all subnets, so data may be slightly out of date from time to time
With the amount of new subnets being added it can be hard to get up to date information across all subnets, so data may be slightly out of date from time to time
ChipForge is a Bittensor subnet (No. 84) that crowdsources hardware (chip) design through blockchain incentives. In essence, it organizes open on-chain “challenges” for designing silicon components (AI accelerators, cryptographic modules, mini-GPUs, RISC-V cores, etc.). Participants (called miners in Bittensor) download a challenge specification (often a Verilog/SystemVerilog problem description), use AI tools or manual engineering to craft a hardware design, and submit their completed Verilog solutions to the network. A set of validators (running industry-standard EDA toolchains like Verilator, Yosys, OpenLane, etc.) automatically evaluates each submission’s functionality, timing, power and area. The highest-scoring designs earn TAO (Bittensor token) rewards. All submitted solutions and scores are recorded on-chain, building a public archive of open-source chip designs.
Modular design challenges: Complex processor designs are broken into smaller “Challenge Bank” tasks (e.g. an ALU block, a mini-GPU kernel) to make collaboration and competition accessible. Each challenge has its own specification (often a PDF spec on GitHub).
Miner submissions: Participants set up a Bittensor wallet and run the ChipForge miner client (a Python application) to fetch active challenges. Miners then submit optimized hardware designs (Verilog/SystemVerilog code and any testbenches) through a secure API.
Validator evaluation: Design submissions are batched and distributed to validator nodes. Validators run the Chipforge EDA Server, which performs logic synthesis, place-and-route, simulation and static timing analysis. They compute multiple metrics (functionality, area, timing, power) for each design.
Reward and archive: ChipForge uses a winner-takes-all mechanism. Only the top-scoring submission (or those beating the previous best) earn the TAO mining reward; all others forfeit their stake. Winning designs are then archived publicly – every design and its score are stored on-chain to build a shared library of next-gen processor components.
In short, ChipForge turns hardware design into a competitive, collaborative game: engineers worldwide co-create and refine open-source chip designs, fueled by token incentives. By merging AI tooling with human expertise, it decentralizes chip design (the first project of its kind) and creates trustless validation for hardware IP.
ChipForge is a Bittensor subnet (No. 84) that crowdsources hardware (chip) design through blockchain incentives. In essence, it organizes open on-chain “challenges” for designing silicon components (AI accelerators, cryptographic modules, mini-GPUs, RISC-V cores, etc.). Participants (called miners in Bittensor) download a challenge specification (often a Verilog/SystemVerilog problem description), use AI tools or manual engineering to craft a hardware design, and submit their completed Verilog solutions to the network. A set of validators (running industry-standard EDA toolchains like Verilator, Yosys, OpenLane, etc.) automatically evaluates each submission’s functionality, timing, power and area. The highest-scoring designs earn TAO (Bittensor token) rewards. All submitted solutions and scores are recorded on-chain, building a public archive of open-source chip designs.
Modular design challenges: Complex processor designs are broken into smaller “Challenge Bank” tasks (e.g. an ALU block, a mini-GPU kernel) to make collaboration and competition accessible. Each challenge has its own specification (often a PDF spec on GitHub).
Miner submissions: Participants set up a Bittensor wallet and run the ChipForge miner client (a Python application) to fetch active challenges. Miners then submit optimized hardware designs (Verilog/SystemVerilog code and any testbenches) through a secure API.
Validator evaluation: Design submissions are batched and distributed to validator nodes. Validators run the Chipforge EDA Server, which performs logic synthesis, place-and-route, simulation and static timing analysis. They compute multiple metrics (functionality, area, timing, power) for each design.
Reward and archive: ChipForge uses a winner-takes-all mechanism. Only the top-scoring submission (or those beating the previous best) earn the TAO mining reward; all others forfeit their stake. Winning designs are then archived publicly – every design and its score are stored on-chain to build a shared library of next-gen processor components.
In short, ChipForge turns hardware design into a competitive, collaborative game: engineers worldwide co-create and refine open-source chip designs, fueled by token incentives. By merging AI tooling with human expertise, it decentralizes chip design (the first project of its kind) and creates trustless validation for hardware IP.
ChipForge’s “product” is not a physical chip but a software protocol and network on Bittensor. It consists of open-source code, servers, and tools that implement the decentralized design workflow. The core deliverables include:
Challenge Server: A Python-based API server that manages each design challenge’s lifecycle (activation, submissions, scoring). It issues challenges to miners and collects submissions.
EDA Server: A backend that runs electronic design automation tools. Validators pull submissions from the challenge server and feed them through this server, which performs synthesis, place-and-route, functional simulation, timing analysis, etc., to score designs.
Miner and Validator Clients: Software packages (Python scripts) that participants install. Miners use start_miner.sh to download challenges and submit solutions. Validators run start_validator.sh to fetch batches and upload scores.
Bittensor Integration: The protocol uses Bittensor wallets/hotkeys to authenticate and stake during submissions. All challenges and scores are stored on the Bittensor chain, and TAO tokens are awarded via the network’s consensus rewards mechanism.
Open-Source Codebase: The entire ChipForge subnet code is publicly available under an MIT license on GitHub. The repository includes the challenge definitions, miner/validator clients, EDA server code, and documentation. For example, the README details the workflow and core components, and the “docs” folder outlines challenge specifications.
The build is primarily Python (the GitHub language stats show ~99% Python) with shell scripts for convenience. It leverages the Bittensor SDK (btcli) for blockchain interaction. In practice, a user sets up a Bittensor wallet, installs the ChipForge package, and runs the miner script; the subnet code handles the rest.
In effect, the product is a decentralized platform that (a) issues hardware design tasks on-chain, (b) validates solutions automatically, and (c) rewards contributors. As a build, it is a running Bittensor subnet (now live as Subnet 84) with a challenge protocol, EDA toolchain integration, and tokenomic incentives.
ChipForge’s “product” is not a physical chip but a software protocol and network on Bittensor. It consists of open-source code, servers, and tools that implement the decentralized design workflow. The core deliverables include:
Challenge Server: A Python-based API server that manages each design challenge’s lifecycle (activation, submissions, scoring). It issues challenges to miners and collects submissions.
EDA Server: A backend that runs electronic design automation tools. Validators pull submissions from the challenge server and feed them through this server, which performs synthesis, place-and-route, functional simulation, timing analysis, etc., to score designs.
Miner and Validator Clients: Software packages (Python scripts) that participants install. Miners use start_miner.sh to download challenges and submit solutions. Validators run start_validator.sh to fetch batches and upload scores.
Bittensor Integration: The protocol uses Bittensor wallets/hotkeys to authenticate and stake during submissions. All challenges and scores are stored on the Bittensor chain, and TAO tokens are awarded via the network’s consensus rewards mechanism.
Open-Source Codebase: The entire ChipForge subnet code is publicly available under an MIT license on GitHub. The repository includes the challenge definitions, miner/validator clients, EDA server code, and documentation. For example, the README details the workflow and core components, and the “docs” folder outlines challenge specifications.
The build is primarily Python (the GitHub language stats show ~99% Python) with shell scripts for convenience. It leverages the Bittensor SDK (btcli) for blockchain interaction. In practice, a user sets up a Bittensor wallet, installs the ChipForge package, and runs the miner script; the subnet code handles the rest.
In effect, the product is a decentralized platform that (a) issues hardware design tasks on-chain, (b) validates solutions automatically, and (c) rewards contributors. As a build, it is a running Bittensor subnet (now live as Subnet 84) with a challenge protocol, EDA toolchain integration, and tokenomic incentives.
ChipForge is developed by the TatsuProject team – the same group behind the Tatsu ecosystem and validator. Key points about the team:
Tatsu Validators: The project is “backed by the Tatsu validator team”, meaning the core network operators of Tatsu are building and running the subnet infrastructure. They manage the servers and ensure uptime.
GitHub Contributors: The ChipForge SN84 GitHub repo lists two core contributors: “atkinson-ai (Atkinson)” and “tatsu-developer (Taτsu)”. These are the developers who authored the codebase. (Their handles suggest one is an AI/hardware researcher and one is the TatsuProject lead.)
Previous Subnets: TatsuProject originally started with other subnets (Identity Verification, Document Understanding) but pivoted. The team notes that ChipForge is now their focus as “the first decentralized hardware design subnet”, replacing the older projects.
Community & Partnerships: While not a formal “team member,” the subnet is open to collaboration with external hardware design experts and AI model developers. The roadmap hints at forging strategic partnerships with semiconductor companies. All community contributors (miners, validators) effectively become part of the team by participating.
Because ChipForge is open-source and decentralized, the “team” extends to any community member who contributes designs or validation. Official communications come from the Tatsu Ecosystem (Twitter/X: @TatsuEcosystem) and documentation on tatsuecosystem.io. (No other full-time staff list is public, aside from the GitHub contributor identities.)
ChipForge is developed by the TatsuProject team – the same group behind the Tatsu ecosystem and validator. Key points about the team:
Tatsu Validators: The project is “backed by the Tatsu validator team”, meaning the core network operators of Tatsu are building and running the subnet infrastructure. They manage the servers and ensure uptime.
GitHub Contributors: The ChipForge SN84 GitHub repo lists two core contributors: “atkinson-ai (Atkinson)” and “tatsu-developer (Taτsu)”. These are the developers who authored the codebase. (Their handles suggest one is an AI/hardware researcher and one is the TatsuProject lead.)
Previous Subnets: TatsuProject originally started with other subnets (Identity Verification, Document Understanding) but pivoted. The team notes that ChipForge is now their focus as “the first decentralized hardware design subnet”, replacing the older projects.
Community & Partnerships: While not a formal “team member,” the subnet is open to collaboration with external hardware design experts and AI model developers. The roadmap hints at forging strategic partnerships with semiconductor companies. All community contributors (miners, validators) effectively become part of the team by participating.
Because ChipForge is open-source and decentralized, the “team” extends to any community member who contributes designs or validation. Official communications come from the Tatsu Ecosystem (Twitter/X: @TatsuEcosystem) and documentation on tatsuecosystem.io. (No other full-time staff list is public, aside from the GitHub contributor identities.)
Tatsu’s public roadmap for ChipForge is ambitious and detailed in their documentation:
Short-term (0–12 months): Focus on expanding digital hardware design capabilities. In particular, they plan to develop real-world chip IP and prototypes. The README states: “Our roadmap includes progressing from design to full-scale fabrication within a year.”. This means they aim to take winning designs (for instance, an AI accelerator module or RISC-V core) all the way through manufacturing, demonstrating end-to-end proof-of-concept chips. Revenue from selling these chips or IP licenses would then be reinvested into the ecosystem.
Challenge Expansion: New categories of challenges will be introduced. The GitHub “Roadmap” section lists “Additional challenge categories” as an upcoming feature. For example, beyond current RISC-V and AI core tasks, they may add challenges for specialized IP blocks (e.g. crypto modules, DSP units) or larger system-on-chip (SoC) integration tasks.
Improved Metrics and Tools: They plan to enhance the evaluation process. The roadmap mentions “Enhanced evaluation metrics” and “Improved toolchain integration”. This could mean refining the scoring (beyond just functionality to weight power and area) and streamlining the validator setup (perhaps integrating cloud synthesis tools or GPU-accelerated simulation).
On-Chain Trading and Partnerships: The Tatsu team’s announcements hint at future features like on-chain trading of chip IPs or co-development platforms. For example, the launch was described as paving the way for “trading of [design] IPs and fabricated chips” and ecosystem buybacks from revenues. While details are sparse, the implication is a longer-term vision where chip designs themselves become tokenized assets.
Version Releases: The first version (v1.0.0) is already out, supporting challenge download, design submission, validation and reward distribution. Future releases will incrementally add features. The GitHub repo’s upcoming milestones likely include full mainnet deployment (already reached) and subsequent improvements per the listed roadmap.
Overall, the roadmap is aggressive: build an open ecosystem for chip design, then leverage that to produce real chips within ~1 year. In parallel, they will keep refining the ChipForge protocol (more tasks, better scoring) and growing the community. All developments are transparent and documented in their public codebase and social channels.
Tatsu’s public roadmap for ChipForge is ambitious and detailed in their documentation:
Short-term (0–12 months): Focus on expanding digital hardware design capabilities. In particular, they plan to develop real-world chip IP and prototypes. The README states: “Our roadmap includes progressing from design to full-scale fabrication within a year.”. This means they aim to take winning designs (for instance, an AI accelerator module or RISC-V core) all the way through manufacturing, demonstrating end-to-end proof-of-concept chips. Revenue from selling these chips or IP licenses would then be reinvested into the ecosystem.
Challenge Expansion: New categories of challenges will be introduced. The GitHub “Roadmap” section lists “Additional challenge categories” as an upcoming feature. For example, beyond current RISC-V and AI core tasks, they may add challenges for specialized IP blocks (e.g. crypto modules, DSP units) or larger system-on-chip (SoC) integration tasks.
Improved Metrics and Tools: They plan to enhance the evaluation process. The roadmap mentions “Enhanced evaluation metrics” and “Improved toolchain integration”. This could mean refining the scoring (beyond just functionality to weight power and area) and streamlining the validator setup (perhaps integrating cloud synthesis tools or GPU-accelerated simulation).
On-Chain Trading and Partnerships: The Tatsu team’s announcements hint at future features like on-chain trading of chip IPs or co-development platforms. For example, the launch was described as paving the way for “trading of [design] IPs and fabricated chips” and ecosystem buybacks from revenues. While details are sparse, the implication is a longer-term vision where chip designs themselves become tokenized assets.
Version Releases: The first version (v1.0.0) is already out, supporting challenge download, design submission, validation and reward distribution. Future releases will incrementally add features. The GitHub repo’s upcoming milestones likely include full mainnet deployment (already reached) and subsequent improvements per the listed roadmap.
Overall, the roadmap is aggressive: build an open ecosystem for chip design, then leverage that to produce real chips within ~1 year. In parallel, they will keep refining the ChipForge protocol (more tasks, better scoring) and growing the community. All developments are transparent and documented in their public codebase and social channels.
Sunday Brief – Feb 22, 2026
A breakthrough week for ChipForge (SN84). We uncovered and fixed a critical deadlock in @Google CoralNPU, and at the same time rebuilt Challenge 0011 into a live bug bounty model powered by new verification infrastructure.
Brief Summary
This week we
Sunday Brief – Feb 15, 2026
A refinement and security week for ChipForge. Following last week's mainnet backend deployment, we focused on polishing the website experience, strengthening API security, and successfully launched the redesigned ChipForge platform.
Brief Summary
This
ChipForge (SN84), reforged — our new site is live
We've rebuilt http://chipforge.io from the ground up — a faster, cleaner experience designed to reflect the scale and ambition of the world's first decenτralized chip foundry.
With engineers competing globally, a completed
Sunday Brief – Feb 8, 2026
A deployment and refinement week for ChipForge. Following last week's finalization push, we deployed critical backend upgrades to mainnet and completed the redesigned ChipForge website, now in final testing before public launch.
Brief Summary
This week
Sunday Brief – Feb 1, 2026
A strong consolidation week for ChipForge. While last week focused on readiness, this week was about finalization, locking the front end, preparing the next Coral NPU challenge, and continuing to strengthen the verification foundation behind it.
Brief
Sunday Brief – Jan 25, 2026
After last week's verification maturity and stress testing, we've completed the full pipeline from challenge creation to production readiness. All core systems are tested and aligned for our first Coral NPU miner challenge.
Brief Summary
This week we
